`timescale 1ns/1ps
`default_nettype none

module global_color_adjust (
    // system signal
    input  wire         I_sclk,
    input  wire         I_rst_n,
    // adjust enable
    input  wire         I_adjust_en,
    // coe
    input  wire [15:0]  I_coe_r0,
    input  wire [15:0]  I_coe_g0,
    input  wire [15:0]  I_coe_b0,
    input  wire [15:0]  I_coe_r1,
    input  wire [15:0]  I_coe_g1,
    input  wire [15:0]  I_coe_b1,
    input  wire [15:0]  I_coe_r2,
    input  wire [15:0]  I_coe_g2,
    input  wire [15:0]  I_coe_b2,
    // input pixel
    input  wire         I_data_en,
    input  wire [15:0]  I_r_in,
    input  wire [15:0]  I_g_in,
    input  wire [15:0]  I_b_in,
    // result
    output wire         O_valid,
    output wire [15:0]  O_r_out,
    output wire [15:0]  O_g_out,
    output wire [15:0]  O_b_out
);
//------------------------Parameter----------------------

//------------------------Local signal-------------------
wire        coe_ack;
wire [15:0] coe_r;
wire [15:0] coe_g;
wire [15:0] coe_b;
reg  [2:0]  coe_sel;

//------------------------Instantiation------------------
// color_adjust
color_adjust color_adjust_inst (
    .I_sclk      ( I_sclk ),
    .I_rst_n     ( I_rst_n ),
    .I_adjust_en ( I_adjust_en ),
    .I_data_en   ( I_data_en ),
    .I_r_in      ( I_r_in ),
    .I_g_in      ( I_g_in ),
    .I_b_in      ( I_b_in ),
    .O_coe_ack   ( coe_ack ),
    .I_coe_r     ( coe_r ),
    .I_coe_g     ( coe_g ),
    .I_coe_b     ( coe_b ),
    .O_valid     ( O_valid ),
    .O_r_out     ( O_r_out ),
    .O_g_out     ( O_g_out ),
    .O_b_out     ( O_b_out )
);

//------------------------Body---------------------------
assign coe_r = coe_sel[0]? I_coe_r0
             : coe_sel[1]? I_coe_r1
             : I_coe_r2;
assign coe_g = coe_sel[0]? I_coe_g0
             : coe_sel[1]? I_coe_g1
             : I_coe_g2;
assign coe_b = coe_sel[0]? I_coe_b0
             : coe_sel[1]? I_coe_b1
             : I_coe_b2;

// coe_sel
always @(posedge I_sclk or negedge I_rst_n) begin
    if (~I_rst_n)
        coe_sel <= 3'b001;
    else if (I_data_en)
        coe_sel <= 3'b001;
    else if (coe_ack)
        coe_sel <= {coe_sel[1:0], coe_sel[2]};
end

endmodule

`default_nettype wire

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